In a conventional data output method for a strobed memory device, data streams are synchronized with one or more strobe signals. Internal data streams are latched to at least one flip-flop for output and are targeted to fire by one or more clock cycles. A pre-driver buffers the output data signals and a large sized main-driver sends the output data signals off chip.
A data window or eye represents the time between the rising and falling edges of the strobe signals. Ideally, an output data-eye will show the complementary rising and falling edges of the data streams to be well balanced. However, in many cases, there can be a mismatch between the rising and falling edges which narrows the data eye. This is undesirable because it limits the amount of time the data is valid.
This mismatch in high and low data propagation times is due to the different physical and electrical characteristics of PMOS and NMOS transistors over variations in process, voltage and temperature (PVT). These variations cannot be removed or completely compensated for over all PVT variations. As clock frequency increases, the mismatch between PMOS and NMOS transistor response becomes even more pronounced.
Referring now to FIG. 1, a block diagram of a conventional data output circuit is shown. FIG. 1 shows a plurality of data input streams 100-0, 100-1, . . . 100-N, a plurality of flip flops 101-0, 101-1, . . . 101-N, a plurality of pre-drivers 102-0, 102-1, . . . 102-N, a plurality of main drivers 103-0, 103-1, . . . 103-N, and a plurality of data output streams 105-0, 105-1, . . . 105-N. Each data input stream 100-0, 100-1, . . . 100-N is input into a respective flip flop 101-0, 101-1, . . . 101-N, each of which outputs to a respective pre-driver 102-0, 102-1, . . . 102-N. Each pre-driver 102-0, 102-1, . . . 102-N outputs to a respective main driver 103-0, 103-1, . . . 103-N, which outputs a data output stream 105-0, 105-1, . . . 105-N.
FIG. 1 also shows high-low toggling data 110 (such as a data strobe), a clock signal 130, and two additional flip flops 111, 112, pre-drivers 112, 122, and main drivers 113, 123, which produce complementary strobe signals S, S#. High-low toggling data 110 is input into flip flops 111, 121. The toggling data is inverted at the input of flip-flop 121 to produce an output signal which is complementary to an output signal of flip-flop 111. The flip-flops 111, 121 output the complementary signals to the inputs of respective pre-drivers 112, 122. Pre-drivers 112, 122 output to the inputs of respective main drivers 113, 123, which output respective complementary strobe signals S, S#. All flip flops 101-0, 101-1, . . . 101-N, 111, 112 are configured to fire responsive to the clock signal 130.
In many cases only one strobe signal S is needed to manage the data streams 105-0, 105-1, . . . 105-N. As a result, the complementary strobe S# circuitry 121, 122, 123 is often omitted.
Under ideal conditions, the rising and falling edges of the strobe signals are matched, as shown in FIG. 2(a). However, as discussed above, PVT variations affect PMOS and NMOS transistors differently. Many times, the edges are skewed as shown in FIGS. 2(b) and 2(c), reducing the data window or eye. As a result data output efficiency is reduced.
There is a need and desire for a method of reliably balancing high and low data outputs in a strobed data circuit, e.g., a memory circuit, so as to maximize the usable data eye. Similarly, there is a need and desire for reliably compensating for an existing mismatch in high and low data outputs.